1. Field of the Invention
The present invention relates to a communication apparatus detecting synchronization using a multi-phase clock, and more particularly to a communication apparatus terminating a clock not required for sampling of a transmission signal.
2. Description of the Related Art
A wireless communication LSI is roughly divided into a radio frequency (RF) LSI and a baseband (BB) LSI. The radio frequency LSI performs analog processing on a signal received through an antenna. The baseband LSI performs digital processing on a transmission signal before modulation or after demodulation.
The high-speed synchronous communication between the radio frequency LSI and the baseband LSI causes a signal delay or a jitter in a transmission line therebetween. At this time, a problem arising when these LSIs are operated independently based on clock signals in asynchronous relation with each other is that an LSI at the receiving side does not receive data correctly. In order to receive data correctly, the LSI at the receiving side controls the phase of a clock used for receiving data. For example, Japanese Patent No. 3792904 discloses a method for the LSI at the receiving side to control the phase of a clock used for receiving data.
FIG. 10 is a block diagram illustrating an exemplary configuration of a receiving device disclosed in Japanese Patent No. 3792904, and more particularly illustrating a demodulation baseband section. A data identification timing signal generation circuit 114 detects a preamble signal based on the received signal and generates a data identification timing signal 115 in synchronism with the timing of detections. In response to the data identification timing signal 115, a circuit operation control signal generator 116 determines whether a preamble signal is received or a signal other than the preamble signal is received. For example, when the preamble signal is received, a binary digital signal of 1 is generated and when a signal other than the preamble signal is received, a binary digital signal of 0 is generated respectively as the circuit operation control signal 117. A clock recovery circuit 122 recovers a symbol clock 123 and a bit clock 124 based on the timing of generating the data identification timing signal 115. A determination unit 125 uses the symbol clock 123 and the bit clock 124 to determine the received signal 111 to output received data 126. Here, using a circuit operation control signal 117 as an enable signal, a clock recovery circuit 122 can perform the above clock recovery only when the preamble signal is received and, when a signal other than the preamble signal is received, can stop the clock recovery by continuously keeping the phase of a clock recovered in the past. By doing so, while the preamble signal is not received, the clock recovery can be turned off, thereby minimizing circuit power consumption.
Note that as a related technique, a digital interface standard between the radio frequency LSI and the baseband LSI and information such as digital interface configurations, symbol rates, and electrical characteristics between the radio frequency LSI and the baseband LSI are disclosed in DRAFT MIPI Alliance Standard for Dual Mode 2.5G/3G Baseband/RFIC Interface, Draft Version 3.09.04, 28 Oct. 2007, http://www.mipi.org/.
However, the receiving device disclosed in Japanese Patent No. 3792904 is configured such that the data identification timing signal generation circuit 114 detects where the preamble is during signal receiving, and the circuit operation control signal 117 triggers the clock recovery circuit 122 to turn on or off. In this way, the clock recovery circuit 122 is operated only when the preamble signal is received. It is therefore necessary to operate the clock recovery circuit 122 to establish synchronization each time the preamble signal is received.
This is because the communication method using the preamble disclosed in Japanese Patent No. 3792904 is described by assuming clock recovery, and thus the master clock frequency and the symbol clock phase for data latch need to be adjusted for each frame. Therefore, although the receiving device disclosed in Japanese Patent No. 3792904 can reduce power consumption by terminating the clock recovery circuit 122 during the period while data is being received, the problem is that clock needs to be recovered to establish synchronization for each frame, thus wasting power.